Sff-ta-100x based multi-mode protocols solid state devices

ABSTRACT

A system includes a storage device; a storage device controller; a first interface configured to connect the storage device controller to the storage device; and a second interface configured to connect the storage device controller to a host device, wherein the storage device is configured to operate in a first mode or a second mode based on a status of a signal at the second interface based on instructions received from the host device.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of U.S. patent application Ser. No.16/509,342, filed Jul. 11, 2019, which claims priority to and thebenefit of U.S. Provisional Patent Application Ser. No. 62/701,494,filed Jul. 20, 2018 and entitled “SFF-TA-100X BASED MULTI-MODE PROTOCOLSFPGA+SOLID STATE DEVICES,” the entire contents of both which areincorporated herein by reference.

FIELD

One or more aspects of embodiments according to the present disclosurerelate to a (SFF)-technology affiliate (TA)-100X based multi-modeprotocols solid state devices.

BACKGROUND

Non-volatile memory (NVM) express (NVMe) is a standard that defines aregister-level interface for host software to communicate with anon-volatile memory subsystem (e.g., a solid state drive (SSD)) over aPeripheral Component Interconnect Express (PCIe) bus. NVMe is analternative to the Small Computer System Interface (SCSI) standard forconnecting and transferring data between a host and a peripheral targetstorage device or system. PCIe-connected NVMe SSDs allow applications tocommunicate directly to storage.

The above information disclosed in this Background section is only forenhancement of understanding of the background of the invention andtherefore it may contain information that does not constitute prior art.

SUMMARY

This summary is provided to introduce a selection of features andconcepts of embodiments of the present disclosure that are furtherdescribed below in the detailed description. This summary is notintended to identify key or essential features of the claimed subjectmatter, nor is it intended to be used in limiting the scope of theclaimed subject matter. One or more of the described features may becombined with one or more other described features to provide a workabledevice.

Aspects of some example embodiments of the present disclosure relate toa SFF-TA-100X based multi-mode protocols solid state devices.

In some embodiments, a system includes a storage device; a storagedevice controller; a first interface configured to connect the storagedevice controller to the storage device; and a second interfaceconfigured to connect the storage device controller to a host device,wherein the storage device is configured to operate in a first mode or asecond mode based on a status of a signal at the second interface basedon instructions received from the host device.

In some embodiments, the storage device is one of a new form factor 1(NF1) solid state drive (SSD), an Ethernet SSD (eSSD), or an embeddedSSD, and the storage device controller is a field programmable gatearray (FPGA) or an application specific integrated circuit (ASIC). Insome embodiments, the first interface is a peripheral componentinterconnect express (PCIe) interface or a U.2 connector, and the secondinterface is a small form factor (SFF)-technology affiliate (TA)-100Xconnector, where X is one of 2, 6, 7, 8, or 9, wherein the storagedevice has one of SFF-8201 2.5″ drive form factor dimensions; SFF-82232.5″ drive form factor with serial connector; SFF-8301 3.5″ drive formfactor dimensions; or SFF-8323 3.5″ drive form dactor with serialconnector.

In some embodiments, the first mode and the second mode of operation ofthe storage device are a non-volatile memory express (NVMe) mode and anNVMe over fabrics (NVMe-oF) mode, respectively. In some embodiments, thesecond interface is a (SFF)-technology affiliate (TA)-1008 connector andthe status of the signal at the second interface is the status of thesignal at a reserved for future use (RFU) pin of the SFF-TA-1008connector, wherein the storage device operates in the NVMe mode when thestatus of the signal at the RFU pin of the SFF-TA-1008 connector is highand the storage device operates in the NVMe-oF mode when the status ofthe signal at the RFU pin of the SFF-TA-1008 connector is low, whereinin each of the NVMe mode and the NVMe-oF mode, the SFF-TA-1008 connectoroperates in X4 single port, X4 dual port, X8 single port, X8 dual port,X16 single port, and X16 dual port mode.

In some embodiments, PCIe signals PERp2, PERn2, PETp2, and PETn2, of theSFF-TA-1008 connector, are configured as control host A and Ethernetport 0, and PCIe signals PERp3, PERn3, PETp3, and PETn3, of theSFF-TA-1008 connector, are configured as control host A and Ethernetport 1, when the storage device and the SFF-TA-1008 connector operate inthe NVMe-oF mode and X4 single port mode, respectively. In someembodiments, PCIe signals PERp1, PERn1, PETp1, and PETn1, of theSFF-TA-1008 connector, are configured as host A and Ethernet port 0, andPCIe signals PERp3, PERn3, PETp3, and PETn3, of the SFF-TA-1008connector, are configured as host B and Ethernet port 1, when thestorage device and the SFF-TA-1008 connector operate in the NVMe-oF andX4 dual port mode, respectively. In some embodiments, PCIe signalsPERp4, PERn4, PETp4, and PETn4, of the SFF-TA-1008 connector, areconfigured as host A and Ethernet port 0, PCIe signals PERp5, PERn5,PETp5, and PETn5 of the SFF-TA-1008 connector are configured as host Aand Ethernet port 1, PCIe signals PERp6, PERn6, PETp6, and PETn6, of theSFF-TA-1008 connector, are configured as host A and Ethernet port 2, andPCIe signals PERp7, PERn7, PETp7, and PETn7, of the SFF-TA-1008connector, are configured as host A and Ethernet port 3, when thestorage device and the SFF-TA-1008 connector operate in the NVMe-oF andX8 single port mode, respectively.

In some embodiments, PCIe signals PERp2, PERn2, PETp2, and PETn2, of theSFF-TA-1008 connector, are configured as host A and Ethernet port 0,PCIe signals PERp3, PERn3, PETp3, and PETn3, of the SFF-TA-1008connector, are configured as host A and Ethernet port 1, PCIe signalsPERp6, PERn6, PETp6, and PETn6, of the SFF-TA-1008 connector, areconfigured as host B and Ethernet port 2, and PCIe signals PERp7, PERn7,PETp7, and PETn7, of the SFF-TA-1008 connector, are configured as host Band Ethernet port 3, when the storage device and the SFF-TA-1008connector operate in the NVMe-oF and X8 single port mode, respectively.

In some embodiments, PCIe signals PERp8, PERn8, PETp8, and PETn8, of theSFF-TA-1008 connector are configured as host A and Ethernet port 0, PCIesignals PERp9, PERn9, PETp9, and PETn9 of the SFF-TA-1008 connector areconfigured as host A and Ethernet port 1, PCIe signals PERp10, PERn10,PETp10, and PETn10, of the SFF-TA-1008 connector, are configured as hostA and Ethernet port 2, PCIe signals PERp11, PERn11, PETp11, and PETn11of the SFF-TA-1008 connector are configured as host A and Ethernet port3, PCIe signals PERp12, PERn12, PETp12, and PETn12 of the SFF-TA-1008connector are configured as host A and Ethernet port 4, PCIe signalsPERp13, PERn13, PETp13, and PETn13 of the SFF-TA-1008 connector areconfigured as host A and Ethernet port 5, PCIe signals PERp14, PERn14,PETp14, and PETn14 of the SFF-TA-1008 connector are configured as host Aand Ethernet port 6, and PCIe signals PERp15, PERn15, PETp15, and PETn15of the SFF-TA-1008 connector are configured as host A and Ethernet port7, when the storage device and the SFF-TA-1008 connector operate in theNVMe-oF and X16 single port mode, respectively.

In some embodiments, PCIe signals PERp8, PERn8, PETp8, and PETn8, of theSFF-TA-1008 connector, are configured as host A and Ethernet port 0,PCIe signals PERp9, PERn9, PETp9, and PETn9, of the SFF-TA-1008connector, are configured as host A and Ethernet port 1, PCIe signalsPERp10, PERn10, PETp10, and PETn10, of the SFF-TA-1008 connector, areconfigured as host B and Ethernet port 0, PCIe signals PERp11, PERn11,PETp11, and PETn11, of the SFF-TA-1008 connector, are configured as hostB and Ethernet port 1, PCIe signals PERp12, PERn12, PETp12, and PETn12,of the SFF-TA-1008 connector, are configured as host A and Ethernet port2, PCIe signals PERp13, PERn13, PETp13, and PETn13, of the SFF-TA-1008connector, are configured as host A and Ethernet port 3, PCIe signalsPERp14, PERn14, PETp14, and PETn14, of the SFF-TA-1008 connector, areconfigured as host B and Ethernet port 2, and the PCIe signals PERp15,PERn15, PETp15, and PETn15, of the SFF-TA-1008 connector, are configuredas host B and Ethernet port 3, when the storage device and theSFF-TA-1008 connector operate in the NVMe-oF and X16 dual port mode,respectively.

In some embodiments, a system includes a computing device; and a storagedevice connected to the computing device via a first interface, whereinthe computing device is configured to operate as a controller of thestorage device, and wherein the computing device is connected to a hostdevice via a second interface.

In some embodiments, the storage device is one of a new form factor 1(NF1) solid state drive (SSD), an Ethernet SSD (eSSD), or an embeddedSSD, and the computing device is a field programmable gate array (FPGA)or an application specific integrated circuit (ASIC), the firstinterface is a peripheral component interconnect express (PCIe)interface or a U.2 connector, and the second interface is a small formfactor (SFF)-technology affiliate (TA)-1008 connector, the storagedevice is configured to operate in a non-volatile memory express (NVMe)mode or an NVMe over fabrics (NVMe-oF) mode, based on a status of asignal at a reserved for future use (RFU) pin of the SFF-TA-1008connector based on instructions received from the host device via ageneral purpose input output (GPIO) connecting to the RFU, and thestorage device operates in the NVMe mode when the status of the signalat the RFU pin of the SFF-TA-1008 connector is high and the storagedevice operates in the NVMe-oF mode when the status of the signal at theRFU pin of the SFF-TA-1008 connector is low, wherein in each of the NVMemode and the NVMe-oF mode, the SFF-TA-1008 connector operates in X4single port, X4 dual port, X8 single port, X8 dual port, X16 singleport, and X16 dual port mode.

In some embodiments, in the X4 single port mode, when the RFU pin of theSFF-TA-1008 connector transitions from low to high status, PCIe signalsPERp2, PERn2, PETp2, and PETn2, of the SFF-TA-1008 connector, transitionfrom being configured as host A, PCIe lane 2 to host A, Ethernet port 0,and PCIe signals PERp3, PERn3, PETp3, and PETn3, of the SFF-TA-1008connector, transition from being configured as host A, PCIe lane 3 tohost A, Ethernet port 1, and wherein in the X4 dual port mode, when theRFU pin of the SFF-TA-1008 connector transitions from low to highstatus, PCIe signals PERp1, PERn1, PETp1, and PETn1, of the SFF-TA-1008connector, transition from being configured as host A, PCIe lane 1 tohost A, Ethernet port 0, and PCIe signals PERp3, PERn3, PETp3, andPETn3, of the SFF-TA-1008 connector, transition from being configured ashost B, PCIe lane 1 to host B, Ethernet port 1.

In some embodiments, in the X8 single port mode, when the RFU pin of theSFF-TA-1008 connector transitions from low to high status, PCIe signalsPERp4, PERn4, PETp4, and PETn4, of the SFF-TA-1008 connector, transitionfrom being configured as host A, PCIe lane 4 to host A, Ethernet port 0,PCIe signals PERp5, PERn5, PETp5, and PETn5, of the SFF-TA-1008connector, transition from being configured as host A, PCIe lane 5 tohost A, Ethernet port 1, PCIe signals PERp6, PERn6, PETp6, and PETn6, ofthe SFF-TA-1008 connector, transition from being configured as host A,PCIe lane 6 to host A, Ethernet port 2, and PCIe signals PERp7, PERn7,PETp7, and PETn7, of the SFF-TA-1008 connector, transition from bringconfigured as host A, PCIe lane 7 to host A, Ethernet port 3, andwherein in the X8 dual port mode, when the RFU pin of the SFF-TA-1008connector transitions from low to high status, PCIe signals PERp2,PERn2, PETp2, and PETn2, of the SFF-TA-1008 connector, transition frombeing configured as host B, PCIe lane 0 to host A, Ethernet port 0, PCIesignals PERp3, PERn3, PETp3, and PETn3, of the SFF-TA-1008 connector,transition from being configured as host B, PCIe lane 1 to host A,Ethernet port 1, PCIe signals PERp6, PERn6, PETp6, and PETn6, of theSFF-TA-1008 connector, transition from being configured as host B, PCIelane 2 to host B, Ethernet port 2, and PCIe signals PERp7, PERn7, PETp7,and PETn7, of the SFF-TA-1008 connector, transition from beingconfigured as host B, lane 3 to host B, Ethernet port 3.

In some embodiments, in the X16 single port mode, when the RFU pin ofthe SFF-TA-1008 connector transitions from low to high status, PCIesignals PERp8, PERn8, PETp8, and PETn8, of the SFF-TA-1008 connector,transition from being configured as host A, PCIe lane 8 to host A,Ethernet port 0, PCIe signals PERp9, PERn9, PETp9, and PETn9, of theSFF-TA-1008 connector, transition from being configured as host A, PCIelane 9 to host A, Ethernet port 1, PCIe signals PERp10, PERn10, PETp10,and PETn10, of the SFF-TA-1008 connector, transition from beingconfigured as host A, PCIe lane 10 to host A, Ethernet port 2, PCIesignals PERp11, PERn11, PETp11, and PETn11, of the SFF-TA-1008connector, transition from being configured as host A, PCIe lane 11 tohost A, Ethernet port 3, PCIe signals PERp12, PERn12, PETp12, andPETn12, of the SFF-TA-1008 connector, transition from being configuredas host A, PCIe lane 12 to host A, Ethernet port 4, PCIe signals PERp13,PERn13, PETp13, and PETn13, of the SFF-TA-1008 connector, transitionfrom being configured as host A, PCIe lane 13 to host A, Ethernet port5, PCIe signals PERp14, PERn14, PETp14, and PETn14, of the SFF-TA-1008connector, transition from being configured as host A, lane 14 to hostA, Ethernet port 6, and PCIe signals PERp15, PERn15, PETp15, and PETn15,of the SFF-TA-1008 connector, transition from being configured as hostA, lane 15 to host A, Ethernet port 7.

In some embodiments, in the X16 dual port mode, when the RFU pin of theSFF-TA-1008 connector transitions from low to high status, PCIe signalsPERp8, PERn8, PETp8, and PETn8, of the SFF-TA-1008 connector, transitionfrom being configured as host A, PCIe lane 4 to host A, Ethernet port 0,PCIe signals PERp9, PERn9, PETp9, and PETn9, of the SFF-TA-1008connector, transition from being configured as host A, PCIe lane 5 tohost A and Ethernet port 1, PCIe signals PERp10, PERn10, PETp10, andPETn10, of the SFF-TA-1008 connector, transition from being configuredas host B, PCIe lane 4 to host B, Ethernet port 0, PCIe signals PERp11,PERn11, PETp11, and PETn11, of the SFF-TA-1008 connector, transitionfrom being configured as host B, PCIe lane 5 to host B, Ethernet port 1,PCIe signals PERp12, PERn12, PETp12, and PETn12, of the SFF-TA-1008connector, transition from being configured as host A, PCIe lane 6 tohost A, Ethernet port 2, PCIe signals PERp13, PERn13, PETp13, andPETn13, of the SFF-TA-1008 connector, transition from being configuredas host A, PCIe lane 7 to host A, Ethernet port 3, PCIe signals PERp14,PERn14, PETp14, and PETn14, of the SFF-TA-1008 connector, transitionfrom being configured as host B, PCIe lane 6 to host B, Ethernet port 2,and PCIe signals PERp15, PERn15, PETp15, and PETn15, of the SFF-TA-1008connector, transition from being configured as host B, PCIe lane 7 tohost B, Ethernet port 3.

In some embodiments, a method of selecting operating mode for a storagedevice, the storage device being connected to a storage devicecontroller via a first interface, wherein the storage device controlleris connected to a host device via a second interface, the methodincludes determining a status of a signal of the second interface;determining an operating mode of the storage device based on the statusof the signal at the second interface; and determining a status of adual port pin of the host device to determine if the storage device isoperating in a single port mode or a dual port mode.

In some embodiments, the storage device is one of a new form factor 1(NF1) solid state drive (SSD), an Ethernet SSD (eSSD), or an embeddedSSD, and the storage device controller is a field programmable gatearray (FPGA) or an application specific integrated circuit (ASIC), thefirst interface is a peripheral component interconnect express (PCIe)interface or a U.2 connector, and the second interface is a small formfactor (SFF)-technology affiliate (TA)-1008 connector, operating modesof the storage device are a non-volatile memory express (NVMe) mode or aNVMe over fabrics (NVMe-oF) mode, the status of the signal at the secondinterface is the status of the signal at a reserved for future use (RFU)pin of the SFF-TA-1008 connector, the storage device operates in theNVMe mode when the status of the signal at the RFU pin of theSFF-TA-1008 connector is high and the storage device operates in theNVMe-oF mode when the status of the signal at the RFU pin of theSFF-TA-1008 connector is low, and the storage device operates in thedual port mode when the status of the dual port pin is low and thestorage device operates in the single port mode when the status of thedual port pin is high.

In some embodiments, the method further includes downloading an NVMe-oFimage or microcode for the dual port mode to the storage device, whenthe storage device is operating in the dual port NVMe-oF mode,downloading an NVMe-oF image or microcode for the single port mode tothe storage device, when the storage device is operating in the singleport NVMe-oF mode, downloading an NVMe image or microcode for the dualport mode to the storage device, when the storage device is operating inthe dual port NVMe mode, and downloading an NVMe image or microcode forthe single port mode to the storage device, when the storage device isoperating in the single port NVMe mode.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of some example embodiments of the presentdisclosure will be appreciated and understood with reference to thespecification, claims, and appended drawings, wherein:

FIG. 1 illustrates a SFF-TA-1008 connector, according to someembodiments of the present disclosure;

FIG. 2A illustrates a block diagram illustrating an example SSD device,according to some embodiments of the present disclosure;

FIG. 2B illustrates another embodiment of the example SSD device of FIG.2A, according to some embodiments of the present disclosure;

FIG. 3 illustrates an SSD device where an SSD and a SSD controller areembedded together, according to some embodiments of the presentdisclosure; and

FIG. 4 illustrates an example method of mode or protocol selection for aSSD device, according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appendeddrawings is intended as a description of some example embodiments of aSFF-TA-100X based multi-mode protocols solid state devices provided inaccordance with the present invention and is not intended to representthe only forms in which the present invention may be constructed orutilized. The description sets forth the features of the presentinvention in connection with the illustrated embodiments. It is to beunderstood, however, that the same or equivalent functions andstructures may be accomplished by different embodiments that are alsointended to be encompassed within the scope of the invention. As denotedelsewhere herein, like element numbers are intended to indicate likeelements or features.

Non-volatile memory (NVM) express (NVMe) is a standard that defines aregister-level interface for host software to communicate with anon-volatile memory subsystem (e.g., a solid state drive (SSD)) over aPeripheral Component Interconnect Express (PCIe) bus. NVMe is analternative to the Small Computer System Interface (SCSI) standard forconnecting and transferring data between a host and a peripheral targetstorage device or system. PCIe-connected NVMe SSDs allow applications tocommunicate directly to storage.

An Ethernet SSD (eSSD) may utilize an SSD (e.g., U.2) connector tointerface with a system via a mid-plane over the PCIe bus. U.2(SFF-8639) is a computer interface for connecting SSDs to a computer. AU.2 connector can support either two Serial Advanced TechnologyAttachment (SATA) or Serial Attached SCSI (SAS) ports and up to fourlanes (X4) of parallel I/O in PCIe SSDs. If unused, the two PCIe lanes 1and 2 may be optionally used as additional SAS ports if required. TheU.2 connector is standardized for NVMe and supports PCIe 3.0 X4,providing, for example, five times the speed of a SATA SSD.

NVMe over fabrics (NVMe-oF) is an extension to the NVMe standardenabling operation over a variety of fabrics (or interconnects) otherthan PCIe. Herein, the term “fabric,” represents a network topology inwhich network nodes can pass data to each other through a variety ofinterconnecting protocols, ports, and switches. For example,Ethernet-attached SSDs may attach directly to a fabric, and in this casethe fabric is the Ethernet.

NVMe-oF enables the use of alternate transports to PCIe that extend thedistances across which an NVMe host device and NVMe storage drive orsubsystem can connect. Therefore, NVMe-oF is a technology specificationdesigned to enable nonvolatile memory express message-based commands totransfer data directly between a host computer and a target solid-statestorage device (e.g., eSSD or NVMe-oF device) or system over a network,such as Ethernet, Fibre Channel (FC) or InfiniBand. When configured tosupport the NVMe-oF standard, a system can support various fabricsincluding not only Ethernet, but also, Fibre Channel, InfiniBand, andother network fabrics. For example, eSSDs may attach directly to afabric, and in this case the fabric is the Ethernet. An eSSD may referto an SSD that may support the NVMe-oF protocols.

Various SSD connectors may be utilized for exchanging data with SSDsincluding, for example, U.2 connectors (24 Giga bites per second (Gbps)is likely to be maximum speed for SAS4 and PCIe generation 4 protocols),or SFF-TA-100X, where X can be 2,6,7,8 etc.

With the advent of 50G and/or 100G Ethernet SSD (eSSD) and PCIe gen 5,U2 connectors may not be capable to scale up. SFF-TA-100X may supportmuch higher data transaction such PCIe gen 5 and beyond. However,SFF-TA-100X may not support multi-mode or protocols such as NVMe orNVMe-oF. Therefore, some example embodiments may include a single commonSFF-TA-100X (e.g., SFF-TA-1008) device which can support multipleprotocols such as NVMe or NVMe-oF and can be used in various products.The SSD devices may include FPGA+SSD, Fabric-attached SSD or eSSD aswell as SSDs.

Some embodiments of the present disclosure include a SFF-TA-100X (e.g.,SFF-TA-1008) device which can support multiple protocols such as NVMe orNVMe-oF. The proposed multi-mode device can support either NVMe orNVMe-oF by detecting information from a known location or “Chassis Type”or “Protocol Selector” pin in the SFF-TA-100X (e.g., SFF-TA-1008)connector.

For example, an SFF-TA-1006 SSD may be used in data centers, forexample, optimized as scalable main storage and acceleration in serverand storage systems. The size of SFF-TA-1006 SSD is 31.5 mm×111.5mm×5.75 or 7.55 mm and supports up to 12W caseless. An SFF-TA-1006 SSDalso supports SFF-TA-1002 1C (e.g., PCIe x4). An SFF-TA-1006 SSDsupports PCIe up to 32 GT/s. An SFF-TA-1006 SSD has high-capacity orhigh-density NVMe form factor, e.g., up to 36 modules across 1U rackspace and/or up to 12 14×18 mm packages per module (e.g., 432packages/U). An SFF-TA-1006 SSD also supports integrated data-centriccomputation and provides case & case-less options.

In some embodiments, the SSD may be SFF-8201 2.5″ drive form factordimensions; SFF-8223 2.5″ drive form factor with serial connector;SFF-8301 3.5″ drive form factor dimensions; or SFF-8323 3.5″ drive formdactor with serial connector. SFF-100x is a series of form factors allusing the SFF-1002 connector.

As another example, FIG. 1 illustrates an SFF-TA-1008 connector. Asshown in FIG. 1, an SFF-TA-1008 connector 100 may be attached to aFPGA+SSD device, and the combination may be applicable to data centers(e.g., 1U and 2U optimized server and storage enclosure). The differentsizes of the SFF-TA-1008-SSD (e.g., FPGA+SSD connected to theSFF-TA-1008 connector) are 7.5×76×104.9 mm that supports up to 25W,7.5×76×142.2 mm that supports up to 35W, 16.8×76×104.9 mm that supportsup to 70W, and 16.8×76×142.2 mm that supports up to 70W. AnSFF-TA-1008-SSD supports SFF-TA-1002 1C, 2C, and/or 4C (e.g., PCIex4-x16). An SFF-TA-1008 SSD supports PCIe gen 5 up to 32 GT/s, 802.3 to112 GT/s. An SFF-TA-1008-SSD has high-capacity and/or high-density NVMeform factor. For example, the 7.5 mm form factor SFF-TA-1008-SSD (e.g.,7.5×76×104.9 mm that supports up to 25W, 7.5×76×142.2 mm that supportsup to 35W) supports up to 48 modules, for example, 104.9 up to 24 14×18mm packages per module (576 / U) or 142.2 up to 48 14×18 mm packages permodule (960/U). For example, the 16.8 mm form factor SFF-TA-1008-SSD(e.g., 16.8×76×104.9 mm that supports up to 70W and 16.8×76×142.2 mmthat supports up to 70W) supports up to 24 modules or up to 48 14×18 mmflash packages per module (960/U). An SFF-TA-1008-SSD supportsdata-centric computation, for example, an SFF-TA-1008-SSD reducespackages to free up space for integrated accelerator. An SFF-TA-1008 SSDmay include a case for electrostatic discharge (ESD) protection andhot-plug support and aligns with ZSFF 223 and ZSFF 224 (Gen-Z ScalableForm Factors). The case may also be used as heat sink or spreader formanaging the thermal.

In some embodiments, in SFF-TA-1008 connector, the reserved for futureuse (RFU) pin may be used as “Chassis Type or Protocol Selector.” Forexample, when the RFU pin of the SFF-TA-1008 connector is low, itrepresents the NVMe protocol or chassis. Alternatively, when the RFU pinis high, the device (e.g., FPGA+SSD connected to the SFF-TA-1008connector) may detect that the device is present in a NVMe-oF chassisand operate accordingly or vice versa. For example, in some embodimentsaccording to the present disclosure, the RFU pin may be redefined byRFU=NVMe-oF mode, to enable an SFF-TA-100X device (e.g., FPGA+SSDconnected to the SFF-TA-1008 connector) to support both the NVMe and theNVMe-oF protocol. For example, a device (e.g., FPGA+SSD connected to theSFF-TA-1008 connector) may be able to operate in different Ethernetspeeds from 50 G up to 100 G or higher, without any changes to theirhardware. For each of the NVMe mode and the NVMe-oF mode of operation ofthe FPGA+SSD connected to the SFF-TA-1008 connector, the SFF-TA-1008connector operates in X4 single port, X4 dual port, X8 single port, X8dual port, X16 single port, and X16 dual port modes.

In some embodiments, if present in the NVMe chassis, the device (e.g.,FPGA+SSD connected to the SFF-TA-1008 connector) will conform to table 2of Enterprise Data Center Small Form Factor specification revision 0.9,as shown below (Table 1). The below table (Table 1) illustrates standardSFF-TA-1008 PCIe lanes connectivity in single and dual portimplementations, if the RFU pin is low or if the device (e.g., FPGA+SSDconnected to the SFF-TA-1008 connector) is present in the NVMe chassis.

TABLE 1 Standard SFF-TA-1008 PCIe lanes connectivity in single and dualport implementations. x4 Single X8 Single x16 Single Port x4 Dual PortPort x8 Dual Port Port (1 port x16 Dual Port PCIe lanes (1 port x4) (2ports x2) (1 port x8) (2 ports x4) x16) (2 ports x8) PERp0, Host A, laneHost A, lane Host A, lane Host A, lane Host A, lane 0 Host A, lanePERn0, 0 0 0 0 0 PETp0, PETn0 PERp1, Host A, lane Host A, lane Host A,lane Host A, lane Host A, lane 1 Host A, lane PERn1, 1 1 1 1 1 PETp1,PETn1 PERp2, Host A, lane Host B, lane Host A, lane Host B, lane Host A,lane 2 Host B, lane PERn2, 2 0 2 0 0 PETp2, PETn2 PERp3, Host A, laneHost B, lane Host A, lane Host B, lane Host A, lane 3 Host B, lanePERn3, 3 1 3 1 1 PETp3, PETn3 PERp4, No connect No connect Host A, laneHost A, lane Host A, lane 4 Host A, lane PERn4, 4 2 2 PETp4, PETn4PERp5, No connect No connect Host A, lane Host A, lane Host A, lane 5Host A, lane PERn5, 5 3 3 PETp5, PETn5 PERp6, No connect No connect HostA, lane Host B, lane Host A, lane 6 Host B, lane PERn6, 6 2 2 PETp6,PETn6 PERp7, No connect No connect Host A, lane Host B, lane Host A,lane 7 Host B, lane PERn7, 7 3 3 PETp7, PETn7 PERp8, No connect Noconnect No connect No connect Host A, lane 8 Host A, lane PERn8, 4PETp8, PETn8 PERp9, No connect No connect No connect No connect Host A,lane 9 Host A, lane PERn9, 5 PETp9, PETn9 PERp10, No connect No connectNo connect No connect Host A, lane Host B, lane PERn10, 10 4 PETp10,PETn10 PERp11, No connect No connect No connect No connect Host A, laneHost B, lane PERn11, 11 5 PETp11, PETn11 PERp12, No connect No connectNo connect No connect Host A, lane Host A, lane PERn12, 12 6 PETp12,PETn12 PERp13, No connect No connect No connect No connect Host A, laneHost A, lane PERn13, 13 7 PETp13, PETn13 PERp14, No connect No connectNo connect No connect Host A, lane Host B, lane PERn14, 14 6 PETp14,PETn14 PERp15, No connect No connect No connect No connect Host A, laneHost B, lane PERn15, 15 7 PETp15, PETn15

In some embodiments, if the device (e.g., FPGA+SSD connected to theSFF-TA-1008 connector) is present in the NVMe-oF chassis, for example,when the RFU pin is high, then the Ethernet ports of the SFF-TA-1008connector will use only PCIe as defined in table 2 below. Currently,there is no standard implementation specified by the NVMe.Org. In someembodiments, the selection of protocol (e.g., NVMe or NVMe-oF) may bedetermined prior to download of the FPGA image. The giga-transceiversmay be used for either PCIe or Ethernet protocol. In such a case, allPCIe ports are capable of communicating to or from a local centralprocessing unit (CPU) of a motherboard and/or a baseboard managementcontroller (BMC) of a switch, and are used as control plane to performany normal PCIe transactions, device initialization and/or for firmwareupgrade between a BMC or a CPU and the device (e.g., SSD).The belowtable (Table 2) illustrates SFF-TA-1008 PCIe lanes connectivity insingle port, dual port implementations & NVMe-oF mode, for example, whenthe RFU pin is high, the device (e.g., FPGA+SSD connected to theSFF-TA-1008 connector) is present in the NVMe-oF chassis.

TABLE 2 SFF-TA-1008 PCIe lanes connectivity in single port, dual portimplementations & NVMe-oF mode by re defining RFU pin. (X4 Single (x4Dual Port) (X8 Single (x8 Dual Port) (x16 Single) Port) → X2 (2 portsx1) + Port) → (1 port → Port → (1 (x16 Dual Single Port and 2 × 25 Gx4) + (2 ports x2) + port x8) + Port) → (2 PCIe 1 × 50 G Ethernet 1 ×100 G 2 × 50 G 2 × 100 G ports x4) + lanes Ethernet Port Ports EthernetEthernet ports Ethernet ports 2 × 100 G PERp0, Host A, lane 0 Host A,lane 0 Host A, lane 0 Host A, lane 0 Host A, lane Host A, lane PERn0, 00 PETp0, PETn0 PERp1, Host A, lane 1 Host A, Host A, lane 1 Host A, lane1 Host A, lane Host A, lane PERn1, Ethernet 0 1 1 PETp1, PETn1 PERp2,Host A, Host B, lane 0 Host A, lane 2 Host A, Host A, lane Host B, lanePERn2, Ethernet 0 Ethernet 0 2 0 PETp2, PETn2 PERp3, Host A, Host B,Host A, lane 3 Host A, Host A, lane Host B, lane PERn3, Ethernet 1Ethernet 1 Ethernet 1 3 1 PETp3, PETn3 PERp4, No connect No connect HostA, Host B, lane 0 Host A, lane Host A, lane PERn4, Ethernet 0 4 2 PETp4,PETn4 PERp5, No connect No connect Host A, Host B, lane 1 Host A, laneHost A, lane PERp5, Ethernet 1 5 3 PETp5, PETn5 PERp6, No connect Noconnect Host A, Host B, Host A, lane Host B, lane PERn6, Ethernet 2Ethernet 2 6 2 PETp6, PETn6 PERp7, No connect No connect Host A, Host B,Host A, lane Host B, lane PERn7, Ethernet 3 Ethernet 3 7 3 PETp7, PETn7PERp8, No connect No connect No connect No connect Host A, Host A,PERn8, Ethernet 0 Ethernet 0 PETp8, PETn8 PERp9, No connect No connectNo connect No connect Host A, Host A, PERn9, Ethernet 1 Ethernet 1PETp9, PETn9 PERp10, No connect No connect No connect No connect Host A,Host B, PERn10, Ethernet 2 Ethernet 0 PETp10, PETn10 PERp11, No connectNo connect No connect No connect Host A, Host B, PERn11, Ethernet 3Ethernet 1 PETp11, PETn11 PERp12, No connect No connect No connect Noconnect Host A, Host A, PERn12, Ethernet 4 Ethernet 2 PETp12, PETn12PERp13, No connect No connect No connect No connect Host A, Host A,PERn13, Ethernet 5 Ethernet 3 PETp13, PETn13 PERp14, No connect Noconnect No connect No connect Host A, Host B, PERn14, Ethernet 6Ethernet 2 PETp14, PETn14 PERp15, No connect No connect No connect Noconnect Host A, Host B, PERn15, Ethernet 7 Ethernet 3 PETp15, PETn15

As discussed above, when the RFU pin of the SFF-TA-1008 connector ishigh, the FPGA+SSD connected to the SFF-TA-1008 connector, operates inthe NVMe-oF mode and when the RFU pin of the SFF-TA-1008 connector islow, the FPGA+SSD connected to the SFF-TA-1008 connector operates in theNVMe mode. As shown in table 2 above, in some embodiments, when thedevice (e.g., FPGA+SSD attached to the SFF-TA-1008 connector) and theSFF-TA-1008 connector are operating in the NVMe-oF and the X4 singleport mode (e.g., X2 Single Port and 1×50 G Ethernet Port), respectively,the PCIe signals PERp2, PERn2, PETp2, and PETn2, of the SFF-TA-1008connector, may be configured as host A and Ethernet port 0, and the PCIesignals PERp3, PERn3, PETp3, and PETn3, of the SFF-TA-1008 connector,may be configured as Ethernet port 1 of host A. Host A is used torepresent or describe the first port of dual port configuration and hostB is used to represent the second port.

As evident from table 1 (NVMe mode) and table 2 (NVMe-oF mode), in someembodiments, in the X4 single port mode, when the RFU pin of theSFF-TA-1008 connector transitions from low (NVMe mode) to (NVMe-of mode)high, e.g., the FPGA+SSD connected to the SFF-TA-1008 connectortransitions from NVMe mode to NVMe-of mode, the PCIe signals PERp2,PERn2, PETp2, and PETn2, of the SFF-TA-1008 connector, transition frombeing configured as host A, PCIe lane 2 to host A, Ethernet port 0, andthe PCIe signals PERp3, PERn3, PETp3, and PETn3, of the SFF-TA-1008connector, transition from being configured as host A, PCIe lane 3 tohost A, Ethernet port 1.

In some embodiments, when the device (e.g., FPGA+SSD connected to theSFF-TA-1008 connector) and the SFF-TA-1008 connector are operating inthe NVMe-oF and X4 dual port mode (e.g., (2 ports x1)+(2×25G EthernetPorts)), respectively, the PCIe signals PERp1, PERn1, PETp1, and PETn1,of the SFF-TA-1008 connector, may be configured as host A and Ethernetport 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3, of theSFF-TA-1008 connector, may be configured as host B and Ethernet port 1.

As evident from table 1 (NVMe mode) and table 2 (NVMe-oF mode), in someembodiments, in the X4 dual port mode, when the RFU pin of theSFF-TA-1008 connector transitions from low (NVMe mode) to (NVMe-of mode)high, e.g., the FPGA+SSD connected to the SFF-TA-1008 connectortransitions from NVMe mode to NVMe-of mode, the PCIe signals PERp1,PERn1, PETp1, and PETn1, of the SFF-TA-1008 connector, transition frombeing configured as host A, PCIe lane 1 to host A, Ethernet port 0, andthe PCIe signals PERp3, PERn3, PETp3, and PETn3, of the SFF-TA-1008connector, transition from being configured as host B, PCIe lane 1 tohost B, Ethernet port 1.

In some embodiments, when the device (e.g., FPGA+SSD connected to theSFF-TA-1008 connector) and the SFF-TA-1008 connector are operating inthe NVMe-oF and X8 single port mode (e.g., (1 port x4) +(1×100 GEthernet)), respectively, the PCIe signals PERp4, PERn4, PETp4, andPETn4, of the SFF-TA-1008 connector, may be configured as host A andEthernet port 0, the PCIe signals PERp5, PERn5, PETp5, and PETn5, of theSFF-TA-1008 connector, may be configured as host A and Ethernet port 1,the PCIe signals PERp6, PERn6, PETp6, and PETn6, of the SFF-TA-1008connector, may be configured as host A and Ethernet port 2, and the PCIesignals PERp7, PERn7, PETp7, and PETn7, of the SFF-TA-1008 connector,may be configured as host A and Ethernet port 3.

As evident from table 1 (NVMe mode) and table 2 (NVMe-oF mode), in someembodiments, in the X8 single port mode, when the RFU pin of theSFF-TA-1008 connector transitions from low (NVMe mode) to (NVMe-of mode)high, e.g., the FPGA+SSD connected to the SFF-TA-1008 connectortransitions from NVMe mode to NVMe-of mode, the PCIe signals PERp4,PERn4, PETp4, and PETn4, of the SFF-TA-1008 connector, transition frombeing configured as host A, PCIe lane 4 to host A, Ethernet port 0, thePCIe signals PERp5, PERn5, PETp5, and PETn5, of the SFF-TA-1008connector, transition from being configured as host A, PCIe lane 5 tohost A, Ethernet port 1, the PCIe signals PERp6, PERn6, PETp6, andPETn6, of the SFF-TA-1008 connector, transition from being configured ashost A, PCIe lane 6 to host A, Ethernet port 2, and the PCIe signalsPERp7, PERn7, PETp7, and PETn7, of the SFF-TA-1008 connector, transitionfrom bring configured as host A, PCIe lane 7 to host A, Ethernet port 3.

In some embodiments, when the device (e.g., FPGA+SSD connected to theSFF-TA-1008 connector) and the SFF-TA-1008 connector are operating inthe NVMe-oF mode and X8 dual port mode (e.g., (1 port x4) +(1×100 GEthernet)), respectively, the PCIe signals PERp2, PERn2, PETp2, andPETn2, of the SFF-TA-1008 connector, may be configured as host A andEthernet port 0, the PCIe signals PERp3, PERn3, PETp3, and PETn3, of theSFF-TA-1008 connector, may be configured as host A and Ethernet port 1,the PCIe signals PERp6, PERn6, PETp6, and PETn6, of the SFF-TA-1008connector, may be configured as host B and Ethernet port 2, and the PCIesignals PERp7, PERn7, PETp7, and PETn7, of the SFF-TA-1008 connector,may be configured as host B and Ethernet port 3.

As evident from table 1 (NVMe mode) and table 2 (NVMe-oF mode), in someembodiments, in the X8 dual port mode, when the RFU pin of theSFF-TA-1008 connector transitions from low (NVMe mode) to (NVMe-of mode)high, e.g., the FPGA+SSD connected to the SFF-TA-1008 connectortransitions from NVMe mode to NVMe-of mode, the PCIe signals PERp2,PERn2, PETp2, and PETn2, of the SFF-TA-1008 connector, transition frombeing configured as host B, PCIe lane 0 to host A, Ethernet port 0, thePCIe signals PERp3, PERn3, PETp3, and PETn3, of the SFF-TA-1008connector, transition from being configured as host B, PCIe lane 1 tohost A, Ethernet port 1, the PCIe signals PERp6, PERn6, PETp6, andPETn6, of the SFF-TA-1008 connector, transition from being configured ashost B, PCIe lane 2 to host B, Ethernet port 2, and the PCIe signalsPERp7, PERn7, PETp7, and PETn7, of the SFF-TA-1008 connector, transitionfrom being configured as host B, lane 3 to host B, Ethernet port 3.

In some embodiments, when the device (e.g., FPGA+SSD connected to theSFF-TA-1008 connector) and the SFF-TA-1008 connector are operating inthe NVMe-oF mode and X16 single port mode (e.g., (1 port x8) +(2×100 GEthernet ports)), respectively, the PCIe signals PERp8, PERn8, PETp8,and PETn8, of the SFF-TA-1008 connector, may be configured as host A andEthernet port 0, the PCIe signals PERp9, PERn9, PETp9, and PETn9, of theSFF-TA-1008 connector, may be configured as host A and Ethernet port 1,the PCIe signals PERp10, PERn10, PETp10, and PETn10, of the SFF-TA-1008connector, may be configured as host A and Ethernet port 2, the PCIesignals PERp11, PERn11, PETp 11, and PETn11, of the SFF-TA-1008connector, may be configured as host A and Ethernet port 3, the PCIesignals PERp12, PERn12, PETp12, and PETn12, of the SFF-TA-1008connector, may be configured as host A and Ethernet port 4, the PCIesignals PERp13, PERn13, PETp13, and PETn13, of the SFF-TA-1008connector, may be configured as host A and Ethernet port 5, the PCIesignals PERp14, PERn14, PETp14, and PETn14, of the SFF-TA-1008connector, may be configured as host A and Ethernet port 6, and the PCIesignals PERp15, PERn15, PETp15, and PETn15 of the SFF-TA-1008 connector,may be configured as host A and Ethernet port 7.

As evident from table 1 (NVMe mode) and table 2 (NVMe-oF mode), in someembodiments, in the X16 single port mode, when the RFU pin of theSFF-TA-1008 connector transitions from low (NVMe mode) to (NVMe-of mode)high, e.g., the FPGA+SSD connected to the SFF-TA-1008 connectortransitions from NVMe mode to NVMe-of mode, the PCIe signals PERp8,PERn8, PETp8, and PETn8, of the SFF-TA-1008 connector, transition frombeing configured as host A, PCIe lane 8 to host A, Ethernet port 0, thePCIe signals PERp9, PERn9, PETp9, and PETn9, of the SFF-TA-1008connector, transition from being configured as host A, PCIe lane 9 tohost A, Ethernet port 1, the PCIe signals PERp10, PERn10, PETp10, andPETn10, of the SFF-TA-1008 connector, transition from being configuredas host A, PCIe lane 10 to host A, Ethernet port 2, the PCIe signalsPERp11, PERn11, PETp11, and PETn11, of the SFF-TA-1008 connector,transition from being configured as host A, PCIe lane 11 to host A,Ethernet port 3, the PCIe signals PERp12, PERn12, PETp12, and PETn12, ofthe SFF-TA-1008 connector, transition from being configured as host A,PCIe lane 12 to host A, Ethernet port 4, the PCIe signals PERp13,PERn13, PETp13, and PETn13, of the SFF-TA-1008 connector, transitionfrom being configured as host A, PCIe lane 13 to host A, Ethernet port5, the PCIe signals PERp14, PERn14, PETp14, and PETn14, of theSFF-TA-1008 connector, transition from being configured as host A, lane14 to host A, Ethernet port 6, and the PCIe signals PERp15, PERn15,PETp15, and PETn15, of the SFF-TA-1008 connector, transition from beingconfigured as host A, lane 15 to host A, Ethernet port 7.

In some embodiments, when the device (e.g., FPGA+SSD connected to theSFF-TA-1008 connector) is operating in the NVMe-oF, X16 dual port mode(e.g., (2 ports x4) +(2×100 G)), the PCIe signals PERp8, PERn8, PETp8,and PETn8, of the SFF-TA-1008 connector, may be configured as host A andEthernet port 0, the PCIe signals PERp9, PERn9, PETp9, and PETn9, of theSFF-TA-1008 connector, may be configured as host A and Ethernet port 1,the PCIe signals PERp10, PERn10, PETp10, and PETn10, of the SFF-TA-1008connector, may be configured as host B and Ethernet port 0, the PCIesignals PERp11, PERn11, PETp11, and PETn11, of the SFF-TA-1008connector, may be configured as host B and Ethernet port 1, the PCIesignals PERp12, PERn12, PETp12, and PETn12, of the SFF-TA-1008connector, may be configured as host A and Ethernet port 2, the PCIesignals PERp13, PERn13, PETp13, and PETn13, of the SFF-TA-1008connector, may be configured as host A and Ethernet port 3, the PCIesignals PERp14, PERn14, PETp14, and PETn14, of the SFF-TA-1008connector, may be configured as host B and Ethernet port 2, and the PCIesignals PERp15, PERn15, PETp15, and PETn15, of the SFF-TA-1008connector, may be configured as host B and Ethernet port 3.

As evident from table 1 (NVMe mode) and table 2 (NVMe-oF mode), in someembodiments, in the X16 dual port mode, when the RFU pin of theSFF-TA-1008 connector transitions from low (NVMe mode) to (NVMe-of mode)high, the PCIe signals PERp8, PERn8, PETp8, and PETn8, of theSFF-TA-1008 connector, transition from being configured as host A, PCIelane 4 to host A, Ethernet port 0, the PCIe signals PERp9, PERn9, PETp9,and PETn9, of the SFF-TA-1008 connector, transition from beingconfigured as host A, PCIe lane 5 to host A and Ethernet port 1, thePCIe signals PERp10, PERn10, PETp10, and PETn10, of the SFF-TA-1008connector, transition from being configured as host B, PCIe lane 4 tohost B, Ethernet port 0, the PCIe signals PERp11, PERn11, PETp11, andPETn11, of the SFF-TA-1008 connector, transition from being configuredas host B, PCIe lane 5 to host B, Ethernet port 1, the PCIe signalsPERp12, PERn12, PETp12, and PETn12, of the SFF-TA-1008 connector,transition from being configured as host A, PCIe lane 6 to host A,Ethernet port 2, the PCIe signals PERp13, PERn13, PETp13, and PETn13, ofthe SFF-TA-1008 connector, transition from being configured as host A,PCIe lane 7 to host A, Ethernet port 3, the PCIe signals PERp14, PERn14,PETp14, and PETn14, of the SFF-TA-1008 connector, transition from beingconfigured as host B, PCIe lane 6 to host B, Ethernet port 2, and thePCIe signals PERp15, PERn15, PETp15, and PETn15, of the SFF-TA-1008connector, transition from being configured as host B, PCIe lane 7 tohost B, Ethernet port 3.

The below table (Table 3) illustrates a status of SFF-TA-1008 connectorPCIe lanes connectivity in single port, dual port implementations & NVMe(when the RFU pin is low) or NVMe-oF (e.g., when the RFU pin is high)mode by re defining the RFU pin.

TABLE 3 SFF-TA-1008 connector PCIe lanes connectivity in single port,dual port implementations & NVMe (when the RFU pin is low) or NVMe-oF(e.g., when the RFU pin is high) mode by re defining the RFU pin. (X4Single Port) à X2 Single Port and (x4 Dual Port) 1 × 50G Ethernet Port(2 ports x1) + 2 × 25G Ethernet Ports RFU = NVMe-oF and DualPortEN# isde- RFU = NVMe-oF and DualPortEN# is SFF-TA Pins PCIe lanes asserted(high) asserted (low) PERp0, PERn0, PETp0, Host A, lane 0 (optionalusing as control Host A, lane 0 (optional using as PETn0 plane) controlplane) PERp1, PERn1, PETp1, Host A, lane 1 (optional using as controlHost A, Ethernet 0 PETn1 plane) PERp2, PERn2, PETp2, Host A, Ethernet 0Host B, lane 0 (optional using as control PETn2 plane) PERp3, PERn3,PETp3, Host A, Ethernet 1 Host B, Ethernet 1 PETn3

FIG. 2A illustrates a block diagram illustrating an example SSD device200, according to some embodiments of the present disclosure. The SSDdevice 200 may include a computing device, for example, a fieldprogrammable gate array (FPGA) 201 connected to a SSD 202 (e.g., a newform factor 1 (NF1) SSD, an eSSD, or an embedded SSD). The FPGA 201 mayoperate as a controller for the SSD 202 and may provide an interfacebetween a SFF-TA-100X connector or interface, for example, a SFF-TA-1008connector 206 and the SSD 202 and a plurality of flash drives, forexample, 203A and 203B. The SFF-TA-1008 connector 206 may be connectedto a motherboard and/or a BMC of a switch of a host device.

The FPGA 201 may interface with the SSD 202 via a PCIe interface 209(e.g., PCIe X8 interface) through ports 207 (e.g., PCIe RP X8 port) and208 (e.g., PCIe RP X4 port) and multiplexers 218A and 218B. For example,the port 207 of FPGA 201 is connected to a multiplexer 218A via PCIe X4buses 216A and 216B. The port 207 of FPGA 201 is connected to amultiplexer 218B via PCIe X4 bus 216E. The port 208 of FPGA 201 isconnected to the multiplexer 218A via PCIe X4 bus 216C and the port 208of FPGA 201 is connected to the multiplexer 218B via PCIe X4 bus 216F.

The multiplexer 218A is connected to the SSD 202 via the PCIe X8interface 209 through a PCIe X8 transmission bus and the multiplexer218B is connected to the SSD 202 via the PCIe X8 interface 209 through aPCIe X8 receive bus. Therefore, the FPGA 201 may transmit data to theSSD 202 via the transmit multiplexer 218A though the ports 207 and 208using the PCIe X4 transmission busses 216A, 216B, and 216C, and the FPGA201 may receive data from the SSD 202 via the receive multiplexer 218Bthough the ports 207 and 208 using the PCIe X4 receive busses 216D,216E, and 216F. Moreover, the port 207 is connected to a high bandwidthmemory (HBM) 220A and the port 208 is connected to another HBM 220B.Each of the HBM 220A and the HBM 220B are connected to a HBM controller222. In some embodiments, the FPGA 701 is also connected to flash drives203A-203B and a clock circuit 214.

The SFF-TA-1008 connector 206 may be connected to the FPGA 201, via twoPCIe X4 ports 204 and 205 through two multiplexers 210 and 212. The PCIeX4 port 204 may transmit signal or packets to a motherboard over amid-plane via the SFF-TA-1008 connector 206 through the multiplexer 210using a PCIe X4 bus and may receive signal or packets from a motherboardover a mid-plane via the SFF-TA-1008 connector 206 through themultiplexer 212 using another PCIe X4 bus. The PCIe X4 port 205 maytransmit signal or packets to a motherboard over a mid-plane via theSFF-TA-1008 connector 206 through the multiplexer 210 using a PCIe X1bus and may receive signal or packets from a motherboard over amid-plane via the SFF-TA-1008 connector 206 through the multiplexer 212using another PCIe X1 bus. The multiplexer 210 may transmit signal tothe SFF-TA-1008 connector 206 via a PCIe X4 bus and the multiplexer 212may receive signal from the SFF-TA-1008 connector 206 via another PCIeX4 bus.

In some embodiments, the RFU pin 224 of the SFF-TA-1008 connector, whichis reserved for future use, is redefined by RFU=NVMe-oF mode, to enablethe SSD 202 to support both NVMe and NVMe-oF protocol. For example, theSSD 202 may be able to operate in different Ethernet speeds from 50 G upto 100 G or higher, without any changes to their hardware based on thestatus (high or low) of the RFU pin 224. When the RFU pin 224 is high,for example, based on the instructions received from the motherboard orthe BMC of a host device (via a general purpose input output (GPIO)connecting to the RFU) via the SFF-TA-1008 connector 206, the SSD 202operates in the NVMe-oF mode, and the FPGA 201 may connect to theSFF-TA-1008 connector using Ethernet port 0 and Ethernet port 1.However, when the RFU pin 224 is low, for example, based on theinstructions received from the motherboard or the BMC of a host device(via a GPIO connecting to the RFU) via the SFF-TA-1008 connector 206,the SSD 202 operates in the NVMe mode, and the FPGA 201 may connect tothe SFF-TA-1008 connector using the PCIe ports 204, 205 and themultiplexers 210 and 212.

FIG. 2B illustrates another embodiment of the example SSD device 200 ofFIG. 2A. The embodiment of FIG. 2B incorporates all the components ofthe embodiment of FIG. 2A, except, in the embodiment of FIG. 2B, thePCIe X8 interface 209 between the FPGA and the SSD 202, is replaced witha U.2 connector. The embodiment of FIG. 2B is also devoid of HBM 220Aand HBM 220B connected to the ports 207 and 208, and the HBM controller222 connected to each of the HBM 220A and the HBM 220B. In theembodiment of FIG. 2B, when the RFU pin 224 is high, i.e., when the SSD202 is operating in the NVMe-oF mode, the FPGA 201 may connect to theSFF-TA-1008 connector using Ethernet port 1 and Ethernet port 2.

FIG. 3 illustrates an SSD device 300 where an SSD 301 and a SSDcontroller 302 are embedded together. The SSD controller 302 may be aFPGA device or an application specific integrated circuit (ASIC). In theSSD device 300, a SFF-TA-1008 connector 304 may be connected to the SSDcontroller 302 via a PCIe X2 port 306 and an Ethernet port 310 (e.g.,Ethernet port 0 and Ethernet port 1). The SSD controller 302 maytransmit or receive signal or packets to a motherboard over a mid-planevia the SFF-TA-1008 connector 304 through the PCIe X2 port 306 and theEthernet port 310. In some embodiments, the RFU pin 308 of theSFF-TA-1008 connector 304, which is reserved for future use, isredefined by RFU=NVMe-oF mode, to enable the SSD 301 to support bothNVMe and NVMe-oF protocol. For example, the SSD 301 may be able tooperate in different Ethernet speeds from 50 G up to 100 G or higher(NVMe-oF mode), without any changes to their hardware based on thestatus (high) of the RFU pin 308. When the RFU pin 308 is high, i.e.,when the SSD 301 is operating in the NVMe-oF mode, the SSD controller302 may connect to the SFF-TA-1008 connector 304 using the Ethernet port310 (e.g., Ethernet port 0 and Ethernet port 1) and may operate indifferent Ethernet speeds from 50 G up to 100 G or higher.

FIG. 4 illustrates an example method of mode or protocol (NVMe orNVMe-oF) selection for a SSD device. The SSD device may be the SSDdevice 200 of FIG. 2A.

In method 400, the device (e.g., the SSD device 200) resets at 401.

At 402, the SSD controller (e.g., FPGA 201) of the SSD device (e.g., SSDdevice 200) checks the status of the RFU pin (e.g., RFU pin 224) of theSFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206) connected at thefront end of the SSD device (e.g., SSD device 200).

If at 402, the status of the RFU pin (e.g. RFU pin 224) is determined tobe high, at 404, the SSD (e.g., SSD 202) connected to the SSD controller(e.g., the FPGA 201), starts to operate in the NVMe-oF mode.

Once the SSD (e.g., SSD 202) starts to operate in the NVMe-oF mode at404, at 406, the SSD controller (e.g., FPGA 201) of the SSD device(e.g., SSD device 200) checks the status of the dual port pin of thehost device connected to the SSD device (e.g., SSD device 200) via thefront end SFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206).

If at 406, the status of the dual port pin of the host device connectedto the SSD device (e.g., SSD device 200) is determined to be low, at408, the SSD (e.g., SSD 202) starts to operate in a dual port NVMe-oFmode, and at 410, the SSD controller (e.g., FPGA 201) downloads NVMe-oFimage or microcode for dual port mode to the SSD (e.g., SSD 202)operating in the dual port NVMe-oF mode, from the host device connectedto the SSD device (e.g., SSD device 200), via the front end SFF-TA-1008connector (e.g., SFF-TA-1008 connector 206).

However, if at 406, the status of the dual port pin of the host deviceconnected to the SSD device (e.g., SSD device 200) is determined to behigh, at 412, the SSD (e.g., SSD 202) starts to operate in a single portNVMe-oF mode, and at 414, the SSD controller (e.g., FPGA 201) downloadsNVMe-oF image or microcode for single port mode to the SSD (e.g., SSD202) operating in the single port NVMe-oF mode, from the host deviceconnected to the SSD device (e.g., SSD device 200), via the front endSFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206).

If at 402, the status of the RFU pin (e.g. RFU pin 224) is determined tobe low, at 416, the SSD (e.g., SSD 202) connected to the SSD controller(e.g., the FPGA 201), starts to operate in the NVMe mode.

Once the SSD (e.g., SSD 202) starts to operate in the NVMe mode at 416,at 418, the SSD controller (e.g., FPGA 201) of the SSD device (e.g., SSDdevice 200) checks the status of the dual port pin of the host deviceconnected to the SSD device (e.g., SSD device 200) via the front endSFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206).

If at 418, the status of the dual port pin of the host device connectedto the SSD device (e.g., SSD device 200) is determined to be low, at420, the SSD (e.g., SSD 202) starts to operate in a dual port NVMe mode,and at 422, the SSD controller (e.g., FPGA 201) downloads NVMe image ormicrocode for dual port mode to the SSD (e.g., SSD 202) operating in thedual port NVMe-oF mode, from the host device connected to the SSD device(e.g., SSD device 200), via the front end SFF-TA-1008 connector (e.g.,SFF-TA-1008 connector 206).

However, if at 418, the status of the dual port pin of the host deviceconnected to the SSD device (e.g., SSD device 200) is determined to behigh, at 424, the SSD (e.g., SSD 202) starts to operate in a single portNVMe mode, and at 426, the SSD controller (e.g., FPGA 201) downloadsNVMe image or microcode for single port mode to the SSD (e.g., SSD 202)operating in the single port NVMe mode, from the host device connectedto the SSD device (e.g., SSD device 200), via the front end SFF-TA-1008connector (e.g., SFF-TA-1008 connector 206).

It will be understood that, although the terms “first”, “second”,“third”, etc., may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer or section from another element, component, region, layer orsection. Thus, a first element, component, region, layer or sectiondiscussed herein could be termed a second element, component, region,layer or section, without departing from the spirit and scope of theinventive concept.

Spatially relative terms, such as “beneath”, “below”, “lower”, “under”,“above”, “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that such spatially relative terms are intended to encompassdifferent orientations of the device in use or in operation, in additionto the orientation depicted in the figures. For example, if the devicein the figures is turned over, elements described as “below” or“beneath” or “under” other elements or features would then be oriented“above” the other elements or features. Thus, the example terms “below”and “under” can encompass both an orientation of above and below. Thedevice may be otherwise oriented (e.g., rotated 90 degrees or at otherorientations) and the spatially relative descriptors used herein shouldbe interpreted accordingly. In addition, it will also be understood thatwhen a layer is referred to as being “between” two layers, it can be theonly layer between the two layers, or one or more intervening layers mayalso be present.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcept. As used herein, the terms “substantially,” “about,” and similarterms are used as terms of approximation and not as terms of degree, andare intended to account for the inherent deviations in measured orcalculated values that would be recognized by those of ordinary skill inthe art.

As used herein, the singular forms “a” and “an” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising”, when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof. As used herein, the term “and/or”includes any and all combinations of one or more of the associatedlisted items. Expressions such as “at least one of,” when preceding alist of elements, modify the entire list of elements and do not modifythe individual elements of the list. Further, the use of “may” whendescribing embodiments of the inventive concept refers to “one or moreembodiments of the present disclosure”. Also, the term “exemplary” isintended to refer to an example or illustration. As used herein, theterms “use,” “using,” and “used” may be considered synonymous with theterms “utilize,” “utilizing,” and “utilized,” respectively.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to”, “coupled to”, or “adjacent to” anotherelement or layer, it may be directly on, connected to, coupled to, oradjacent to the other element or layer, or one or more interveningelements or layers may be present. In contrast, when an element or layeris referred to as being “directly on”, “directly connected to”,“directly coupled to”, or “immediately adjacent to” another element orlayer, there are no intervening elements or layers present.

Any numerical range recited herein is intended to include all sub-rangesof the same numerical precision subsumed within the recited range. Forexample, a range of “1.0 to 10.0” is intended to include all subrangesbetween (and including) the recited minimum value of 1.0 and the recitedmaximum value of 10.0, that is, having a minimum value equal to orgreater than 1.0 and a maximum value equal to or less than 10.0, suchas, for example, 2.4 to 7.6. Any maximum numerical limitation recitedherein is intended to include all lower numerical limitations subsumedtherein and any minimum numerical limitation recited in thisspecification is intended to include all higher numerical limitationssubsumed therein.

The electronic or electric devices and/or any other relevant devices orcomponents according to embodiments of the present disclosure describedherein may be implemented utilizing any suitable hardware, firmware(e.g. an application-specific integrated circuit), software, or acombination of software, firmware, and hardware. For example, thevarious components of these devices may be formed on one integratedcircuit (IC) chip or on separate IC chips. Further, the variouscomponents of these devices may be implemented on a flexible printedcircuit film, a tape carrier package (TCP), a printed circuit board(PCB), or formed on one substrate. Further, the various components ofthese devices may be a process or thread, running on one or moreprocessors, in one or more computing devices, executing computer programinstructions and interacting with other system components for performingthe various functionalities described herein. The computer programinstructions are stored in a memory which may be implemented in acomputing device using a standard memory device, such as, for example, arandom access memory (RAM). The computer program instructions may alsobe stored in other non-transitory computer readable media such as, forexample, a CD-ROM, flash drive, or the like. Also, a person of skill inthe art should recognize that the functionality of various computingdevices may be combined or integrated into a single computing device, orthe functionality of a particular computing device may be distributedacross one or more other computing devices without departing from thespirit and scope of the exemplary embodiments of the present disclosure.

Although exemplary embodiments of a SFF-TA-100X based multi-modeprotocols solid state devices have been specifically described andillustrated herein, many modifications and variations will be apparentto those skilled in the art. Accordingly, it is to be understood that toa SFF-TA-100X based multi-mode protocols solid state devices constructedaccording to principles of this disclosure may be embodied other than asspecifically described herein. The inventive concept is also defined inthe following claims, and equivalents thereof.

What is claimed is:
 1. A system comprising: a storage device; a storagedevice controller; a first interface configured to connect the storagedevice controller to the storage device; and a second interfaceconfigured to connect the storage device controller to a host device,wherein the storage device is configured to operate in a first mode or asecond mode based on a status of a signal at the second interface basedon instructions received from the host device.